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Figure 22.1. PCNT Overview
CMU (conceptual)
LFACLK
Clock
switch
Peripheral bus
Inverter
Inverter
Pulse Width
Filter
Quadrature
decoder
Edge
detector
OVR_SINGLE
EXTCLK_SINGLE
1
EXTCLK_QUAD
CNT
TOP
TOPB
22.3.1 Pulse Counter Modes
The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked
single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode
(EXTCLKQUAD). The following sections describe operation of each of the three modes and how they
are enabled. Input timing constraints are described in Section 22.3.3 (p. 312) and Section 22.3.4 (p.
313) .
22.3.1.1 Single Input Oversampling Mode
This mode is enabled by writing OVSSINGLE (0x1) to the MODE field in the PCNTn_CTRL register and
disabled by writing DISABLE (0x0) to the same field. The LFACLK is configured from the registers in
the Clock Management Unit (CMU), Chapter 11 (p. 92) .
The optional pulse width filter is enabled by writing 1 to the FILT bit in the PCNTn_CTRL register.
Additionally, the PCNTn_S0IN input may be inverted, so that falling edges are counted, by writing 1 to
the EDGE bit in the PCNTn_CTRL register.
PCNTn_S0IN is the only observed input in this mode. This input is sampled by the LFACLK and the
number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT. The counter
may be configured to count down by writing 1 to the CNTDIR bit in PCNTn_CTRL. Default is to count up.
Only the underflow (UF) and overflow (OF) interrupt flags are set in this mode.
22.3.1.2 Externally Clocked Single Input Counter Mode
This mode is enabled by writing EXTCLKSINGLE (0x2) to the MODE field in the PCNTn_CTRL register
and disabled by writing DISABLE (0x0) to the same field. The external pin clock source must be
configured from the registers in the CMU (Chapter 11 (p. 92) ).
Positive edges on PCNTn_S0IN are used to clock the counter. PCNTn_S1IN is ignored in this mode. As
the LFACLK is not used in this mode, the PCNT module can operate in EM3. Like in the oversampling
mode, the counter may be configured to count down by writing 1 to the CNTDIR bit in the PCNTn_CTRL
register. Default is to count up.
The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads
is capable of removing some unwanted noise. However, this mode may be susceptible to spikes and
2011-04-12 - d0001_Rev1.10
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